Covered 0.3 Description:
Verilog code coverage analysis utility.
Covered is a Verilog code-coverage utility used for Design Verification which is capable of performing line, toggle, combinational logic and finite state machine (FSM) coverage analysis. Verilog source files are parsed along with VCD dumpfiles to create Coverage Description Database (CDD) files which can be merged with other CDD files generated from the same design and/or have reports generated from them through the use of the merge and report commands, respectively.
ConclusionTo conclude Covered works on Linux operating system and can be easily downloaded using the below download link according to GNU Public License license.
Covered was filed under the Science category and was reviewed in softlookup.com and receive 2.1/5 Score.
Covered has been tested by our team against viruses, spyware, adware, trojan, backdoors and was found to be 100% clean. We will recheck Covered when updated to assure that it remains clean.
Covered user ReviewPlease review Covered application and submit your comments below. We will collect all comments in an effort to determine whether the Covered software is reliable, perform as expected and deliver the promised features and functionalities.
Popularity 4.2/10 - Downloads - 200 - Score - 2.1/5
|License:||GNU Public License|
|File size:||Not specified|