Covered 0.3 Description:
Verilog code coverage analysis utility. Covered is a Verilog code-coverage utility used for Design Verification which is capable of performing line, toggle, combinational logic and finite state machine (FSM) coverage analysis. Verilog source files are parsed along with VCD dumpfiles to create Coverage Description Database (CDD) files which can be merged with other CDD files generated from the same design and/or have reports generated from them through the use of the merge and report commands, respectively.
This program gives you all the features you need to create basic- to intermediate-level vector graphics, including bezier curves, lines, rulers, and m (Not Specified)