Ver 1.3.36-2 Description:
Structural Verilog compiler for UNIX operating systems. Structural Verilog compiler for UN*X operating systems. Some synthesizable behavioral constructs are now supported. An event simulator (vsim) is included for testing of logic designs. A cycle simulation compiler (cyco/csim) is included which can compile netlists into fast levelized C code. Cyco can also generate ABEL netlists that may be used for FPGA generation. GTKWave, a fully-featured wave viewer is quite functional now. (requires GTK+ -1.2.0 or greater).
This program gives you all the features you need to create basic- to intermediate-level vector graphics, including bezier curves, lines, rulers, and m (Not Specified)