Ver (1.3.36-2) Free Download


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Category: Science 
Publisher: Tony Bybell      More titles >>
Last Updated: 5/19/2003
Requirements: Not specified
License: GNU Public License
Operating system: Linux
Hits: 1106
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Ver  1.3.36-2 Description:

Structural Verilog compiler for UNIX operating systems. Structural Verilog compiler for UN*X operating systems. Some synthesizable behavioral constructs are now supported. An event simulator (vsim) is included for testing of logic designs. A cycle simulation compiler (cyco/csim) is included which can compile netlists into fast levelized C code. Cyco can also generate ABEL netlists that may be used for FPGA generation. GTKWave, a fully-featured wave viewer is quite functional now. (requires GTK+ -1.2.0 or greater).

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